The present invention relates generally to the multiplexing of digital information in communications systems, and more specifically to a SONET multiplexed communications system having an architecture that permits greater levels of integration.
Synchronous Optical NETwork (SONET) multiplexed communications systems are known that employ time division multiplex switching techniques to route digital information between a plurality of communications paths. An architecture of a conventional SONET multiplexed communications system includes at least one Time Slot Interchanger (TSI) that receives digital information contained in respective time slots from a plurality of SONET input signal paths. The TSI temporarily stores the digital information received during each time slot, and subsequently retransmits that information during another time slot associated with at least one SONET output signal path. In this way, the TSI operates as a cross-switch to route digital information from a SONET input signal path associated with a first time slot to at least one SONET output signal path associated with a second time slot.
In the conventional SONET multiplexed system, the SONET input signal paths may operate at clock rates that are different from the clock rates of the TSI and/or the SONET output signal paths. Further, transport overhead information included in the digital information of SONET output signals may be placed in locations that are different from the transport overhead information included in corresponding SONET input signals. For at least these reasons, pointer processors typically included in the SONET signal paths comprise respective First-In First-Out (FIFO) buffers to compensate for timing variations in the SONET input and output signals that may result from the different clock rates of the SONET input and output signal paths and the different locations of the transport overhead information included in the SONET input and output signals.
One drawback of the conventional SONET multiplexed system is that a significant amount of logic circuitry is required to implement the respective pointer processors in the SONET signal paths. This can be problematic when implementing SONET multiplexed systems on integrated circuits because increased amounts of logic circuitry mean increased die sizes, which can increase manufacturing costs.
It would therefore be desirable to have a SONET multiplexed system for routing digital information between a plurality of SONET input signal paths and a plurality of SONET output signal paths. Such a SONET multiplexed system would have an architecture permitting greater levels of integration.